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PCI EXPRESSTM JITTER ATTENUATOR
ICS874003-05 Features
* * * * * * * * * * * *
Three differential LVDS output pairs One differential clock input CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Input frequency range: 98MHz to 128MHz Output frequency range: 98MHz to 320MHz VCO range: 490MHz - 640MHz Supports PCI-Express Spread-Spectrum Clocking High PLL bandwidth allows for better input tracking PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant 0C to 70C ambient operating temperature Full 3.3V operating supply Available in lead-free (RoHS 6) packages
General Description
The ICS874003-05 is a high performance Differential-to-LVDS Jitter Attenuator designed for HiPerClockSTM use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-05 has a bandwidth of 6.2MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL requirements.
ICS
The ICS874003-05 uses IDT's 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
Pin Assignment
F_SEL[2:0] Function Table
Inputs F_SEL2 0 (default) 1 0 1 0 1 0 1 F_SEL1 0 (default) 0 1 1 0 0 1 1 F_SEL0 0 (default) 0 0 0 1 1 1 1 Outputs QA[0:1], nQA[0:1] /2 /5 /4 /2 /2 /5 /4 /4 QB0, nQB0 /2 /2 /2 /4 /5 /4 /5 /4
QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA
ICS874003-05
20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View
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Block Diagram
OEA Pullup F_SEL2:0 Pulldown
3
QA0
/5 /4 /2 (default)
CLK Pulldown
nQA0
QA1
nCLK Pullup
Phase Detector
VCO
490 - 640MHz
3
nQA1
M = /5 (fixed)
/5 /4 /2 (default)
QB0
nQB0
MR Pulldown
OEB Pullup
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Table 1. Pin Descriptions
Number 1, 20 2, 19 3, 4 Name QA1, nQA1 VDDO QA0, nQA0 Output Power Output Type Description Bank A differential output pair. LVDS interface levels. Output supply pins. Bank A differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inverted outputs (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Frequency select pin for QAx/nQAx and QB0/nQB0 outputs. LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Core supply pin. Pullup Pulldown Pullup Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Pullup Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are active. When LOW, the QB0/nQB0 outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. Bank B differential output pair. LVDS interface levels.
5
MR
Input
Pulldown
6, 9, 16 7 8 10 11 12 13 14 15 17, 18
F_SEL0, F_SEL1, F_SEL2 nc VDDA VDD OEA CLK nCLK GND OEB nQB0, QB0
Input Unused Power Power Input Input Input Power Input Output
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
Table 3. Output Enable Function Table
Inputs OEA 0 1 (default) OEB 0 1 (default) Outputs QA[0:1], nQA[0:1] High Impedance Enabled QB0, nQB0 High Impedance Enabled
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO (LVDS) Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 86.7C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.16 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 75 16 75 Units V V V mA mA mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage OEA, OEB Input High Current F_SEL0, F_SEL1, F_SEL2, MR OEA, OEB IIL Input Low Current F_SEL0, F_SEL1, F_SEL2, MR VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A
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Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol IIH Parameter CLK Input High Current nCLK CLK IIL VPP VCMR Input Low Current nCLK Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVDS DC Characteristics, VDD = VDDO = = 3.3V 5%, TA = 0C to 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.20 1.35 Test Conditions Minimum 275 Typical 375 Maximum 485 50 1.50 50 Units mV mV V mV
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Table 5. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol fMAX tjit(cc) tsk(o) tsk(b) tR / tF odc Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE 4 Output Skew; NOTE 4, 5 Bank Skew; NOTE 4, 6 Output Rise/Fall Time Output Duty Cycle 100MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) tj Phase Jitter Peak-to-Peak; NOTE 1, 3 125MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 250MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 100MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) tREFCLK_HF_RMS Phase Jitter RMS; NOTE 2, 3 125MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 250MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 100MHz output, Low Band: 10kHz - 1.5MHz tREFCLK_LF_RMS Phase Jitter RMS; NOTE 2, 3 125MHz output, Low Band: 10kHz - 1.5MHz 250MHz output, Low Band: 10kHz - 1.5MHz Bank A 20% to 80% 200 47 13.54 Test Conditions Minimum 98 Typical Maximum 320 35 145 55 600 53 Units MHz ps ps ps ps % ps
13.13
ps
12.87
ps
1.22
ps
1.17
ps
1.11
ps
0.25 0.22 0.22
ps ps ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Peak-to-peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. See IDT Application Note PCI Express Reference Clock Requirements, and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
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Parameter Measurement Information
VDD
SCOPE
3.3V5% POWER SUPPLY + Float GND -
nCLK
V
PP
VDD, VDDO
Qx
VDDA CLK
Cross Points
V
CMR
LVDS
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
nQA0 QA0 nQA1 QA1
nQAx, nQB0 QAx, QB0
tcycle n
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
tsk(b)
Bank Skew
Cycle-to-Cycle Jitter
nQx Qx nQy Qy
nQAx, nQB0 QAx, QB0
t PW
t
PERIOD
tsk(o)
odc =
t PW t PERIOD
Output Skew
Output Duty Cycle/Pulse Width/Period
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tcycle n+1
x 100%
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Parameter Measurement Information, continued
VDD
nQAx, nQB0
80%
80% VOD
DC Input
out
QAx, QB0
20% tR tF
20%
LVDS
out
VOS/ VOS
Output Rise/Fall Time
Offset Voltage Setup
VDD

out
DC Input
LVDS
100
VOD/ VOD out
Differential Output Voltage Setup
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Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS874003-05 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 2. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 R4 120
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK Zo = 60
CLK
nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver
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Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
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Schematic Example
Figure 5 shows an example of ICS874003-05 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. Two examples of LVDS terminations are shown in this schematic. The input is driven either by a 3.3V LVPECL driver or a 3.3V LVCMOS.
ICS874003-05
Figure 5. ICS874003-05 Schematic Example
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PCI Express Application Note
PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is:
Ht ( s ) = H3 ( s ) x [ H1 ( s ) - H2 ( s ) ]
The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is:
Y ( s ) = X ( s ) x H3 ( s ) x [ H1 ( s ) - H2 ( s ) ]
In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz Nyquist (High Band). The below plots show the individual transfer functions as well as the overall transfer function Ht. The respective -3 dB pole frequencies for each transfer function are labeled as F1 for transfer function H1, F2 for H2, and F3 for H3. For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.
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Magnitude of Transfer Functions - PCIe Gen 1 0
F1: 2.2e+007 F2: 1.5e+006 F3: 1.5e+006
-10
-20 Mag (dB)
-30
-40 H1 H2 H3 Ht=(H1-H2)*H3 10
4
-50
-60 3 10
10 10 Frequency (Hz)
5
6
10
7
PCIe Gen 1 Magnitude of Transfer Function
Magnitude of Transfer Functions - PCIe Gen 2A 0
Magnitude of Transfer Functions - PCIe Gen 2B 0
F1: 1.6e+007 F2: 5.0e+006 F3: 1.0e+006
F1: 1.6e+007 F2: 8.0e+006 F3: 1.0e+006
-10
-10
-20 Mag (dB)
-20 Mag (dB)
-30
-30
-40 H1 H2 H3 Ht=(H1-H2)*H3 10
4
-40 H1 H2 H3 Ht=(H1-H2)*H3 10
4
-50
-50
-60 3 10
10 10 Frequency (Hz)
5
6
10
7
-60 3 10
10 10 Frequency (Hz)
5
6
10
7
PCIe Gen 2A Magnitude of Transfer Function
PCIe Gen 2B Magnitude of Transfer Function
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS874003-05. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS74003-05 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 16mA) = 315.315mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.875mW
Total Power_MAX = 315.3mW + 259.9mW = 575.2mW *
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.575W * 86.7C/W = 119.9C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board.
Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 86.7C/W 1 82.4C/W 2.5 80.2C/W
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Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 86.7C/W 1 82.4C/W 2.5 80.2C/W
Transistor Count
The transistor count for ICS874003-05 is: 1418
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number 874003BG-05LF 874003BG-05LFT Marking 874003BG-05LF 874003BG-05LF Package "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Contact Information:
www.IDT.com
Sales
800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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